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      Buscas relacionadas: Avaliações da empresa Apple | Vagas da empresa Apple | Salários da empresa Apple | Benefícios da empresa Apple
      Entrevistas da empresa AppleEntrevistas do cargo de Design Verification Engineer da empresa AppleEntrevista da empresa Apple


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      Entrevista para Design Verification Engineer

      20 de jul. de 2020
      Candidato(a) sigiloso(a) à entrevista
      Livorno
      Nenhuma oferta
      Experiência neutra
      Entrevista difícil

      Candidatura

      Candidatei-me por indicação de um funcionário. O processo levou 5 meses. Fui entrevistado pela Apple (Livorno) em jun. de 2020

      Entrevista

      Applied through referral in the middle of lockdown in Europe. Had a first chat with HR, went through my CV and my motivations. After 3 weeks got a phone interview. This was inline whith the position requirements: a lot of SystemVerilog and UVM questions in a row. Not much time to answer but they were all quicj questions. After another 3 weeks I had the 5h30m interview, it was online due to Covid19. 6 interviewers, one after the other. All of them were from different sites than the one I applied for. Each of them looked to be specialized on some particular topic. Had questions on UVM and SystemVerilog, but also questions on algorithms and mixed-signal verification (not among requirements). Interviewers were quite fast, not much time to think on a problem. Didn't look like any of them was happy to be there interviewing me and only one of them showed interest in what I've done or would want to do. The rest of them were just asking questions. I understand they work for Apple but maybe they would need a better approach with applicants.

      Perguntas de entrevista [1]

      Pergunta 1

      45 mins phone interview: task vs function associative arrays packed vs unpacked scoreboard structures `uvm_do sequencer structure coverage: code vs functional functional cov: module and collector number of automatic bins for an int code coverage metrics uvm_object vs uvm_component concurrent vs immediate assertions 5hrs interview: reg model in uvm adapter and predictor scoreboard structure how to use some of the phases exercise on how to verify a DUT that gets data from 2 sensors list of quick questions on systemverilog how to verify req ack interfaces, also which assertions how to verify in a mixed signal enviroment find errors in given code (like missing "virtual" in parent/child sequences, or missing "automatic" in for loop with fork join_none) optimized way to generate Fibonacci's sequence recursive function to generate a given sequence shortest path algorithm: given starting point and destination point in a 2D matrix, get the shortest path from one to the other, including some non valid coordinates what kind of functional coverage I have done, how I've done scoreboards, some other questions about CV experiences
      Responder à pergunta
      17

      Outras avaliações de entrevista de vagas de Design Verification Engineer da empresa Apple

      Entrevista para Design Verification Engineer

      11 de mar. de 2026
      Candidato(a) sigiloso(a) à entrevista
      San Diego, CA
      Nenhuma oferta
      Experiência positiva
      Entrevista difícil

      Candidatura

      Fiz uma entrevista na empresa Apple (San Diego, CA).

      Entrevista

      There were 1 screening and 6 panel rounds and it was difficult especially UVM part also they AMBA protocols basic design questions like fsm fifo and all and more focus on constraints

      Perguntas de entrevista [1]

      Pergunta 1

      UVM based questions and Assertions and constraints
      Responder à pergunta

      Entrevista para Design Verification Engineer

      24 de abr. de 2026
      Candidato(a) sigiloso(a) à entrevista
      Sunnyvale, CA
      Nenhuma oferta
      Experiência neutra
      Entrevista fácil

      Candidatura

      Candidatei-me online. Fui entrevistado pela Apple (Sunnyvale, CA) em mar. de 2026

      Entrevista

      I had a screening round that started directly without any introduction. I was asked questions about my resume, mainly about my projects. After that, I was given a coding question.

      Entrevista para Design Verification Engineer

      1 de fev. de 2026
      Candidato(a) sigiloso(a) à entrevista
      San Jose, CA
      Nenhuma oferta
      Experiência neutra
      Entrevista com nível médio de dificuldade

      Candidatura

      Fiz uma entrevista na empresa Apple (San Jose, CA).

      Entrevista

      first asking about the tool experience, asking about UVM knowledge like how and when to connect the sequencer and driver and what is their handshake , how do you deal with CDC problems, how to do the STA analysis, then final having a coding question

      Perguntas de entrevista [1]

      Pergunta 1

      implementation of driver class based on the figure they gave
      Responder à pergunta