Phone interview
Design gates using CMOS transistors.
Build gates using 2-to-1 muxes.
Write a verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency.
The number of states required for a sequence recognizer.

Question

Phone interview
Design gates using CMOS transistors.
Build gates using 2-to-1 muxes.
Write a verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency.
The number of states required for a sequence recognizer.

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