How does sizing effect the speed, power and area of the gates? low power analysis and Importance of Static Cmos Race conditions , assign, case,casex,casez , gave an rtl coding problem and told to design in vhdl, verilog and system verilog. Then explain how the code is interpreted in every language with respect to design . Difference between blocking / non blocking, reg/wire/logic in terms of memory storing? Packed and unpacked multi dimensional array differences and their memory allocations? C++ Concepts of class, structure and virtual functions? STA/DTA analysis ,step-up /hold time based questions Busses in arm processors Questions on interface, modports and clocking blocks how to find or debug a race and glitch in simulation, most importantly version and the build of the vcs tool and linux commands Basic of uvm, system-verilog- functions, tasks,classes, and why interface is a separate class name (why it had to be uniquely designed)