Candidatei-me online. O processo levou 1 semana. Fui entrevistado pela Cirrus Logic (Dallas, TX) em fev. de 2016
Entrevista
I had applied for the position in December. Got a call in February. I had prepared for more detailed SystemVerilog questions, but the phone interview was mostly basic and application-oriented - DSP, analog, OOPs concepts, and verification fundamentals. The interviewer was satisfied with most of my answers. I thought it went well. They didn't apparently. Got a reject in 2 days.
Perguntas de entrevista [2]
Pergunta 1
For a six-deep FIFO with one (and two clocks), push and pop operations, what specific test cases will you use to verify the design?