Pergunta de entrevista da empresa AMD
Generate a 2Ghz clock and code the FSM (The one with the asynchronous reset) in verilog.
Resposta da entrevista
Sigiloso
16 de ago. de 2022
Verilog isn't really taught in school so I didn't answer the question.
Generate a 2Ghz clock and code the FSM (The one with the asynchronous reset) in verilog.
Sigiloso
Verilog isn't really taught in school so I didn't answer the question.