Candidatei-me por meio de uma faculdade ou universidade. O processo levou 1 semana. Fui entrevistado pela Qualcomm (Bengaluru) em ago. de 2020
Entrevista
asked questions on VLSI physical design, questions on cmos inverter, different cells used in physical design, what projects and experience i have in this field, some questions related to digital design
4 interviewers.
Basics of physical design /cpu architecture/experience based questions/tcl scripting/timing analysis/block closure /techniques/previous wrk exp/ drc analysis related questions/ tool related questions/ example
Based questions “how would you solve this?” Kind of questions
Perguntas de entrevista [1]
Pergunta 1
Explain the challenges involved in previous tapeout
Candidatei-me online. Fui entrevistado pela Qualcomm (Austin, TX) em set. de 2025
Entrevista
One hour and loop with 5 people each round focusing on eache step of physical design flow and cadence tools. I have a thesis on RISC V low voltage pd so they asked about that more
Fiz uma entrevista na empresa Qualcomm (San Diego, CA).
Entrevista
Application via Qualcomm careers or referral.
Recruiter may reach out for basic screening:
Your background, tools used (ICC2, PrimeTime, RedHawk, etc.)
Areas of expertise: floorplanning, CTS, routing, STA, DRC, EMIR, etc.
Experience with multi-VDD, ECOs, hierarchical designs, colored flows, etc.
Technical Phone Interviews (1–2 rounds)
Each round typically lasts 45–60 minutes.
Perguntas de entrevista [1]
Pergunta 1
Walk me through how you approach floorplanning for a block.
How do you handle placement of macros and standard cells around them?
What considerations go into designing a power grid?
How do you handle multi-VDD domains or level shifters?
What are tie-high and tie-low cells and where are they used?