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Standard FPGA questions - state machines, hold/setup time etc.
Sigiloso
It's essential to demonstrate that you can really go deep... there are plenty of followup questions and (sometimes tangential) angles to explore. There's a lot of FPGA Design Engineer experts who've worked at Xilinx, who provide this sort of practice through mock interviews. There's a whole list of them curated on Prepfully. prepfully.com/practice-interviews