Pergunta de entrevista da empresa Marvell Technology
Verilog tasks and functions, FSM Design, FIFO Depth, some system verilog questions.
Resposta da entrevista
Sigiloso
4 de out. de 2016
task can have delay, even,t, or timing control constructs. functions returns a single value and must have at least one input. For FSM, use 1-hot encoding. FIFO: use grey-code. System Verilog: use Assertions