Pergunta de entrevista da empresa Intel Corporation
Write the Verilog code for a D-Flip Flop.
Resposta da entrevista
Sigiloso
20 de jul. de 2015
wire d, clk; reg q; always @(posedge clk) q <= d;
1
Write the Verilog code for a D-Flip Flop.
Sigiloso
wire d, clk; reg q; always @(posedge clk) q <= d;