1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it.
2nd round: gave a problem and had to create FSM and verilog.

Question

1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it.
2nd round: gave a problem and had to create FSM and verilog.

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