Genral questions
1 setup time hold time
2 verilog basics
verilog caculating (a+b)/2 or (a+b+c+d)/4, how to round
3 what 's the use of arbitrary
4 vending machine state machine
5 architecture pipeline
Candidatei-me por meio de uma faculdade ou universidade. O processo levou 1 dia. Fui entrevistado pela Ambarella em mar. de 2014
Entrevista
Phone interview, approximately 1 hour. First the director introduced what his group is doing and asked one of my course project. Then he requested to write Verilog codes, including switching a and b in one clock cycle, explaining blocking and non-blocking, and implementing FSM of a pattern detector.
