Candidatei-me online. O processo levou 1 dia. Fui entrevistado pela Analog Bits (Mountain View, CA) em jun. de 2012
Entrevista
The process begins with a phone interview with some general questions about CMOS transistors. Some of the questions require grabbing a pencil and a piece of paper. The answers that you provide are submitted to the hiring manager, who then decides whether you will be called back for an on-site interview.
Perguntas de entrevista [2]
Pergunta 1
How would you size the NMOS and PMOS transistors in an inverter to obtain equal rise and fall times?
How would you draw the CMOS schematic for a 2-input NAND gate? What would the pull-up and pull-down networks look like? If VDD and VSS are switched, what gate is formed?
Candidatei-me por meio de recrutador(a). O processo levou 2 dias. Fui entrevistado pela Analog Bits (San Francisco, CA) em mar. de 2015
Entrevista
I didn't make it passed the phone interview. The man who interviewed me was very polite - I think he was a different person than the one who did phone interviews with other people on here - but I failed the last question, which is the same one everyone else on here mentioned. I can't remember it exactly but I've come back to see if I can answer it. I'll update if I figure out how to explain it.
Perguntas de entrevista [1]
Pergunta 1
Mobility questions, how to build a NAND and NOR gate, and the one I failed was about a transistor in cutoff where you need the drain voltage.
