Candidatei-me por meio de recrutador(a). Fui entrevistado pela Broadcom (Santa Clara, CA) em jul. de 2016
Entrevista
Interviewed with two managers, 5 IC Design Engineers. Total 7 people
The interview process took the whole day from 10AM to 4:30 PM. One manager took me for lunch after his interview session and then I came back for next round.
Perguntas de entrevista [1]
Pergunta 1
-High/low pass filter passive and active design and frequency domain
-What is PLL and draw the diagram, graph, and explanations
-Draw the logic circuit diagram for Half/full adder
-Draw circuit to divide a clock into two
-How to debug on coding based on memory address/content info.
-Calculate voltage from a circuit
-Transmission line and its resistance related question.
-Embedded board power failure trouble shooting
-Algorithms questions for binary search tree and other questions.
Basically to write down your thoughts on a white board and explain the result/thinking process.
Candidatei-me online. Fui entrevistado pela Broadcom em jan. de 2026
Entrevista
Phone call with hiring manager, followed by full day of onsite technical interviews with senior engineers. Onsite interviews were easy and fun, office was pretty depressing. Regret going through the process.
Perguntas de entrevista [1]
Pergunta 1
standard things such as CDC, FIFOs, logic optimization.
As expected. Multiple rounds to go through . Overall good experience. Need to go through phone screening first and then get to onsite. Interviewers were nice and knowledgeable. I guess it also depends on the group you’re interviewing for.
Perguntas de entrevista [1]
Pergunta 1
How do you design asynchronous fifo and related timing checks ?
Candidatei-me online. O processo levou 2 meses. Fui entrevistado pela Broadcom em jan. de 2023
Entrevista
Phone screening then 6-7 rounds of in person interview. Mostly asked about my experience, my understanding of the job role, and a couple rounds of technical questions. Only a couple interviewers had a script or notes so they were highly conversational.
Perguntas de entrevista [1]
Pergunta 1
What is the difference between := and :/ in SystemVerilog?