Perguntas de entrevista de vagas de Rtl Design Engineer da empresa Infosys

What is RTL (Register Transfer Level)? Difference between combinational and sequential logic. What are blocking (=) and non-blocking (<=) assignments? When do you use each? Explain synchronous vs asynchronous reset — which is preferred and why? What is the difference between wire and reg in Verilog? What are latches, and how are they inferred unintentionally