Candidatei-me por indicação de um funcionário. O processo levou 2 semanas. Fui entrevistado pela Intel Corporation (Boston, MA) em mar. de 2016
Entrevista
The process took 2 weeks. One phone screen interview and Onsite (Intel Hudson Campus) - 6:1 one-on-one. 9 am to 3 pm. The interviewers will be spending some time describing environmental context, and will look to evaluate your problem-solving capability when introduced to new concepts. They are very friendly and will help you get the answer out of you.
Perguntas de entrevista [1]
Pergunta 1
Phone screen: difference between FF and latch, charge sharing dynamic logic circuits, Which is faster pmos or nmos and why, driver in one end and receiver at the other end separated by transmission wire how would you design? ( ie pi model ), how would you design AND gate using NOR, MOSFET characteristics ( Saturation, cut off)
Onsite -
9am-10am : Manufacturing Test Environment
10-11am: ATPG-based test content & debug
11am-noon: Functional Content Development & Validation
1:15-2:30pm: Silicon debug & triage
2:30-3pm: Technical Q&A
Candidatei-me de outra forma. O processo levou 4 dias. Fui entrevistado pela Intel Corporation (Atlanta, GA) em fev. de 2018
Entrevista
This was for a 6 month Co-op. I had one phone call interview. No further rounds in the selection criteria. They gave a week before the call. The interview was a mixture of technical and non-tech question. It lasted for 30 mins.
Perguntas de entrevista [1]
Pergunta 1
Mosfet modes, NOr gate logic, interconnect delay, RC delay, logic design using de-morgans, diff between nand and nor gates, diff between latches and FFs.
Candidatei-me online. O processo levou 4 semanas. Fui entrevistado pela Intel Corporation (Austin, TX) em mar. de 2016
Entrevista
I got a call and after a week time, I was called for onsite interview. It was a day long interview. It went well, but I got a reject. They did not respond to any
Perguntas de entrevista [1]
Pergunta 1
Mostly the basics of VLSI, Logic design, Circuit Design
