Candidatei-me por meio de recrutador(a). O processo levou 2 semanas. Fui entrevistado pela Intel Corporation (Cupertino, CA) em abr. de 2016
Entrevista
The interview was considered easier than other companies, basically walked through the resume and asked questions for the work I was done in the previous companies. People were very polite.
Perguntas de entrevista [1]
Pergunta 1
SystemVerilog assertion and functional coverage coding.
Candidatei-me online. Fiz uma entrevista na empresa Intel Corporation.
Entrevista
1 Screening Round and 4 Technical rounds and 1 HR Round conducted. In 1 week interview scheduled and offer released in 2 to 3 weeks.
Questions from system verilog and uvm, Project related question which have hands on experience
Candidatei-me online. Fui entrevistado pela Intel Corporation em jan. de 2023
Entrevista
UVM question System Verilog Question AMBA Buses, AXI, AHB and APB When and how would you perform a factory override? Describe the differences between components and objects in UVM. How do you connect a DUT interface to a UVM component? Which UVM phase do you integrate to for phase runs for test cases? How would you reduce the time it takes to initiate a UVM run phase?
Perguntas de entrevista [1]
Pergunta 1
describe UVM Phases and difference bet run phase and main phase
Candidatei-me online. O processo levou 2 meses. Fui entrevistado pela Intel Corporation (Santa Clara, CA) em jan. de 2023
Entrevista
Ask me Verilog, SystemVerilog, UVM basics, C/C++ problem-solving questions, and about my resume projects. Focus on digital design, verification concepts, coding logic, and real-time debugging approaches.more on resume focused and old projects in detailed manner.
