Candidatei-me online. Fui entrevistado pela Intel Corporation (Hillsboro, OR) em out. de 2018
Entrevista
One screening phone call and 6 on campus rounds including hr round
Verilog, architecture, power, timing, circuit and hr at intel oregon campus
Interviewed at CPU design team. Offered physical design position.
Candidatei-me pessoalmente. O processo levou 1 dia. Fui entrevistado pela Intel Corporation (Santa Clarita, CA) em jan. de 2016
Entrevista
Got selected for a screening interview after an in-person interaction at an info session. After one screening interview, got a call for an on-site after 2 months. It was a full day grilling interview @ Santa Clara, CA. There were four rounds - 3 technical and 1 behavioral.
First round was behavioral,
then next round was logic design/comp arch mixed,
next purely digital logic design,
and last one was purely comp arch.
Perguntas de entrevista [3]
Pergunta 1
Describe a situation when you would use a Direct mapped cache over a set associative cache.
Draw a state diagram for a given pattern. If even number if 0's come as input, then the output is asserted on every even consecutive 1.
If odd number if 0's come as input, then the output is asserted on every odd consecutive 1.
Candidatei-me por indicação de um funcionário. O processo levou 4 semanas. Fui entrevistado pela Intel Corporation em dez. de 2015
Entrevista
Applied through employee referral program. Cleared Phone Interview and was called for on-site. Phone Interview: It was a very easy interview. Basics of computer architecture and programming were asked. On-site Interview: It was a four round interview. Mainly focused on the resume, logic design and programming skills. Also had a behavioural round. Interview experience was quite good.
Perguntas de entrevista [1]
Pergunta 1
Many questions are framed out of my resume in almost all rounds.
