Candidatei-me por meio de uma faculdade ou universidade. O processo levou 1 dia. Fui entrevistado pela Qualcomm (Hyderābād) em jul. de 2018
Entrevista
The written test can be aced with practice.
Aptitude consists of 20 (10 of them were data interpretation, rest of 10 were quant questions.
Coding- Requires a good experience in C, Data structures.
Core- Digital ( 7 questions) , Oscillators ( 3 questions) , Microcontroller (3 ) , Basic analog electronics like Bjt , diodes ( 3 questions)
The interview took around for 45 mins. It will be easy if u have good command over the projects which u have done. Questions will be decided based on your answers.
Perguntas de entrevista [1]
Pergunta 1
Describe Oscillator principle, PLL, CMOS circuits, Verilog code of SRAM, latch vs flipflop, sequential circuit vs combinational circuit, Wein bridge oscillator, Best of NAND VS NOR, scale yourself 0-10 in python, Biggest challenge u faced, What do u know about the company and what do u like to know about the company?
It was on campus hiring. It consists of an online assessment and resume screening, followed by 3 rounds of interviews, out of which 2 were technical and 1 was HR.
Candidatei-me por meio de recrutador(a). Fiz uma entrevista na empresa Qualcomm (Hsinchu).
Entrevista
The interview process spanned 4 days with one 1–2 hour session per day. Each round began with a 30-minute discussion on my college projects, followed by deep dives into Computer Architecture (CPU Design, Cache ＤDesign, etc.). One of the sessions also included a simple whiteboard coding question.
Perguntas de entrevista [1]
Pergunta 1
Cache Design (calculating cache bits involves breaking down the CPU address into Tag, Index, and Offset field)
Fiz uma entrevista na empresa Qualcomm (Bengaluru).
Entrevista
The interviewer was friendly and created a supportive atmosphere. They offered constructive hints when I got stuck, showing they were focused on my thought process, which made for a positive experience.
Perguntas de entrevista [1]
Pergunta 1
They asked questions on STA,my projects, Verilog case statements
