Had a phone interview followed by 3 rounds of onsite interview. Few questions on verilog coding, state machine to realize time domain crossing between clock domains, layout practises to minimize diffucion cap/power, leakage paths in SRAM, latchup, effect of temperature on MOS, combinational gate realizations etc..Also some questions on the projects mentioned in the resume.

The interviewer was very cooperative and polite. He asked simple digital design questions and sram memory. Prepare well about memories. Also he asked about dynamic circuits and domino effect. Started from basics questions and taught the things i did not answer. I was bit under qualifies for the position. Clear your basics.