What are CDC techniques you know? Explain fast to slow, slow to fast, edge, toggle, pulse?
2. What CDC issue you faced?
3. Explain Sync and Async reset? Explain Reset Domain Crossing?
4. If an asynchronous reset from asynchronous domain is used as a synchronous reset in other clock domain. How will you handle it?
5. Explain latch based clock gating
6. If 2 clocks are muxed using control signal, how will you handle it?
7. Calculate Depth
Wr = 100Mhz, Rd = 50Mhz, Burst = 120
8. What are timing constraints have you used while doing synthesis?
9. Sequence detector - 1001 with overlapping using moore - Verilog code
10. Sequence detector - 1011 with overlapping using mealy - Verilog code
11. Explain RISC-V Architecture, what is your role? Bypass and stall operations, wbmux features
12. How will it be realised with hardware?
Two states - a & b, initial state is a - if ctrl is 0 it remains in a else go to b(op-1). If it's in state b, if ctrl is 0 it remains in b else go to a (op- 1).
13. Write pseudo code for Fibonacci sequence
14. CPU is received interrupts pulse from different IPs, how it will samples inside CPU? We don't have any idea at what rate I am receiving that pulse. But CPU need to find that pulse.
15. Write the equations for setup and hold time. Why hold time does not depend on the clock?
16. Given one STA problem, calculate maximum clock frequency and combo delay.
Tse, Th, Tcq, Tskew given
17. Issues related to convergence, what is convergence?
18. Related to Lint issues, how to fix combo loops?
19. Which FSM style mostly used in industry? How will declare FSM states? What is difference between one hot and binary encoding? Which is better to use and why?
