Candidatei-me por meio de uma faculdade ou universidade. O processo levou 5 dias. Fui entrevistado pela Signalchip Innovations (Bengaluru) em set. de 2020
Entrevista
Pretty hard. Lot of expectations. Very hard to crack. Cover all topics in fundamentals of electronics like analog, digital, signals and embedded, and many more. Around 7 rounds of rigorous interview at different levels.
Candidatei-me por meio de uma faculdade ou universidade. O processo levou 1 dia. Fui entrevistado pela Signalchip Innovations (Bengaluru) em set. de 2023
Entrevista
I applied through campus placement. The first round was an online test, followed by a coding round and finally interview. The interview lasted for 2 hours. First they asked some aptitude questions and they moved on to digital electronics covering number system, adders and mux etc. . Then questions about charging circuits were asked(RC).
Perguntas de entrevista [1]
Pergunta 1
Aptitude questions on factorials and optimizing solutions.
Numbers systems.
Questions related to Mux.
RC charging circuits and time constants.
Questions based on sampling frequency.
Candidatei-me por meio de uma faculdade ou universidade. O processo levou 1 dia. Fui entrevistado pela Signalchip Innovations (Bengaluru) em set. de 2023
Entrevista
In depth questions about digital and signal processing domain related questions were asked. Little analog op amp as well. Some ways of applying multiplexers and pipelining based questions as well
Perguntas de entrevista [1]
Pergunta 1
posedge detector , negedge detector how to do plus some aptiude questions. Some ways of applying multiplexers and pipelining based questions as well
Candidatei-me por meio de uma faculdade ou universidade. Fiz uma entrevista na empresa Signalchip Innovations.
Entrevista
it was part of our campus placement. Interviewer asked me questions on digital electronics, verilog, networks. Interviewer asked me all the basic questions on verilog, digital, networks. It was a easy interview but i could not clear all the rounds.
Perguntas de entrevista [1]
Pergunta 1
verilog code for d flip flop with asynchrounous input, race conditions in verilog, difference between latch and flip flop etc
