Candidatei-me pessoalmente. O processo levou 4 semanas. Fui entrevistado pela Synopsys (Bengaluru) em dez. de 2018
Entrevista
I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.
Perguntas de entrevista [1]
Pergunta 1
I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.
Fiz uma entrevista na empresa Synopsys (Canonsburg, PA).
Entrevista
There were several stages to the interview process. Required a lot of time, but in the end, it was well worth the effort. The interview panel was very supportive and encouraging.
The interview process was seamless, featuring a moderate level of questions. The supportive demeanor of the interviewer enhanced the overall experience, making it smooth and conducive to a positive interaction.
Perguntas de entrevista [1]
Pergunta 1
It covered concepts of Digital Circuits, VLSI Design. Combinational vs Sequential circuits, FFs, FSM.
Candidatei-me por meio de uma faculdade ou universidade. Fui entrevistado pela Synopsys (Bengaluru) em set. de 2022
Entrevista
The Interview was of 3 rounds.
1. Basic Introduction and 1 technical question by the Manager.
2. Technical round by a technical lead.
3. Technical round by another technical lead.
Perguntas de entrevista [1]
Pergunta 1
If there are setup and hold violations and you are at the last stage what would you choose to fix either setup? or hold? and why?
