Pergunta de entrevista da empresa NVIDIA
The first one was about implementing a NOT gate with MUX.
Resposta da entrevista
Sigiloso
1 de fev. de 2011
If you use logic 1s and 0s, and a 2-1 MUX with inputs A, B, selector S, and output F, you can tie A high and B low, let S be the inverter input, and F be the inverter output.
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