Eassy and logica more questions related to system verilog and digital electronics. Some basic questions from UVM. AXI , APB protocols related questions in detail like wait and non wait scenario in APB .

Hiring process is very smooth and HRs will provide required information about your queries. Interview experience is very nice and know about the project you have done and basics on the Systemverilog and UVM

Telophonic interviewAll basics with detailed information and need in depth knowledge required and the interview process took 3personsons in series and it took 3hours to complete : the position of experience as required two years and requirements are verilog, system verilog, uvm , digital concepts