Candidatei-me online. O processo levou 2 semanas. Fui entrevistado pela NVIDIA (Tel Aviv-Yafo) em jan. de 2025
Entrevista
I was asked to implement a 4-bit priority encoder using basic gates , and if i want to add one more bit how many gates i must add? and then to implement an SR flip-flop using D flip-flops — first with asynchronous Set, and then with asynchronous Reset.
Perguntas de entrevista [1]
Pergunta 1
I was asked to implement a 4-bit priority encoder using basic gates , and if i want to add one more bit how many gates i must add? and then to implement an SR flip-flop using D flip-flops — first with asynchronous Set, and then with asynchronous Reset.
Candidatei-me por indicação de um funcionário. Fui entrevistado pela NVIDIA (Tel Aviv-Yafo) em mai. de 2026
Entrevista
two stages, first was personal interview about personal project. the second are question about SR FF, design and solve any edge cases. at the end there was a quick overall review
The interview was coordinated via email with the recruiter. It was a one-hour session conducted on Microsoft Teams. About 15 minutes were dedicated to introductions between the interviewer and myself. The rest of the time was spent on a technical Logic Design question, which I will detail below. After about a week, I received an email stating they had decided not to move forward with my candidacy. Overall, it was a fine experience.
Perguntas de entrevista [1]
Pergunta 1
I was asked to implement an SR Flip-Flop using only a specific set of components. This was followed by questions about minimizing the design and re-implementing it using alternative components.
Candidatei-me online. O processo levou 4 semanas. Fui entrevistado pela NVIDIA (Tel Aviv-Yafo) em out. de 2025
Entrevista
After an initial phone screening with HR, I completed a first technical interview conducted by the team manager together with an engineer from the team, focusing on my background and technical skills.
Perguntas de entrevista [1]
Pergunta 1
You have a module that gets 4 input bits and returns the number of lower bits that are logic ‘1’, along with a valid bit. Expand it to 16 bits.
