Pipelining Hazards?
Perguntas de entrevista de Cpu Design Engineer
85 Perguntas de entrevista compartilhadas pelos candidatos | cpu design engineer
Where do you see yourself in 5 years?
Draw a state diagram for a given pattern. If even number if 0's come as input, then the output is asserted on every even consecutive 1. If odd number if 0's come as input, then the output is asserted on every odd consecutive 1.
Do you know anything about RISC Architecture?
What is cache
Describe a situation when you would use a Direct mapped cache over a set associative cache.
Regarding CPU Clock Signals and Timing Analysis.
What are some ways for error testing/handling in software?
compare tradeoffs of 10 wide vs. 4x 2.5 wide parallel transistors. Made me think.
Have you had experience in CPU physical layout design?
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