In a synthesis process, when you find a problematic route, how can you solve it?
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FPGA designers that use Verilog are typically not good at using object oriented languages like System Verilog.
How would you design an FPGA to prevent bit flipping in a space radiation environment?
So tell me about you? Why do you want to work at Netlist?
do you allow to work in Canada
they asked about projects I involved and my roles and responsibilities. the tools used and debugging using tools. real-time issues faced and their solution.
How to use stack and heap in C programming language?
How do you pass timestamp register from one clock domain to another.
Design and verify a simplified "router".
Standard FPGA questions - state machines, hold/setup time etc.
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